Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs

Authors:
Miguel L. Silva;Joao Canas Ferreira
Affiliations:
FEUP/DEEC, Spain;FEUP/DEEC and INESC Porto, Spain
Venue:
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Year:
2005

Citing 0
Cited 2

Support for partial run-time reconfiguration of platform FPGAs

Journal of Systems Architecture: the EUROMICRO Journal
Modern development methods and tools for embedded reconfigurable systems: A survey

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

The paper describes the organization and use of a pipeline that is tightly-coupled to the CPU inside a platform FPGA with support for dynamic partial reconfiguration. It describes the overall hardware system organization and the pipeline structure, and presents the associated development environment and run-time support system, including the support for dynamically changing pipeline implementations and altering the operations of a pipeline stage.