String matching on multicontext FPGAs using self-reconfiguration
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Introducing ReConfigME: An Operating System for Reconfigurable Computing
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Support for partial run-time reconfiguration of platform FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A multilayer framework supporting autonomous run-time partial reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform
IEICE - Transactions on Information and Systems
Operating System Support for Difference-Based Partial Hardware Reconfiguration
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Exploiting dynamic reconfiguration of platform FPGAs: implementation issues
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Implementation of a FIR filter on a partial reconfigurable platform
KES'06 Proceedings of the 10th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part III
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Reconfigurable computing based on partial reconfiguration of field programmable gate arrays (FPGAs) is yet to move to the mainstream of computing. Hardware devices that support such reconfiguration are now available but no readily available software exists to generate the required partial bitstreams. The JPG tool described in this paper is a Java-based partial bitstream generator designed to fit within the standard Xilinx FPGA design flow. JPG, based on the Xilinx JBits API, is able to generate partial bitstreams for Xilinx Virtex devices based on data extracted from the standard Xilinx CAD tool flow.