Low-energy FPGAs: architecture and design
Low-energy FPGAs: architecture and design
Configuration relocation and defragmentation for run-time reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Platform-independent methodology for partial reconfiguration
Proceedings of the 1st conference on Computing frontiers
Design flow for embedded FPGAs based on a flexible architecture template
Proceedings of the conference on Design, automation and test in Europe
FaRM: fast reconfiguration manager for reducing reconfiguration time overhead on FPGA
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM
Microprocessors & Microsystems
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A novel bitstream generation algorithm and its software implementation are introduced. Although this tool was developed for the configuration of AMDREL FPGA reconfigurable platform, it could be used to program any other compatible device. This tool is the only one known academic implementation for FPGA configuration with such features. Among them are the run-time-, partial- and dynamic-reconfiguration, the memory management, the bitstream compression and encryption, the read-back technique, the bitstream reallocation, the used low-power techniques as well as the Graphical User Interface.