FaRM: fast reconfiguration manager for reducing reconfiguration time overhead on FPGA

Authors:
François Duhem;Fabrice Muller;Philippe Lorenzini
Affiliations:
University of Nice-Sophia Antipolis - LEAT/CNRS;University of Nice-Sophia Antipolis - LEAT/CNRS;University of Nice-Sophia Antipolis - LEAT/CNRS
Venue:
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Year:
2011

Citing 3
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Abstract

In this paper, we present a fast ICAP controller providing high-speed configuration and easy-to-use readback capabilities, reducing configuration overhead as much as possible. In order to enhance performance, FaRM uses techniques such as DMA, ICAP overclocking, bitstream pre-load into controller and bitstream compression, using an evolution of the Run Length Encoding algorithm. We also propose a reconfiguration overhead estimation model which gives a good idea of the overhead. This approach is tested with an AES encryption/decryption architecture. With proper ICAP overclocking to 200 MHz, we are able to reach the ICAP upper bound throughput of 800 MB/s.