Communications of the ACM
JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Using PARBIT to Implement Partial Run-Time Reconfigurable Systems
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
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The effective use of dynamic reconfiguration requires the designer to address many implementation issues. The market introduction of feature-full platform FPGAs equipped with embedded CPU blocks expands the number of situations where dynamic reconfiguration may be applied to improve overall performance and logic utilization. The paper compares the design of two similar systems supporting dynamic reconfiguration and the issues that were addressed in their implementation. The first system supports 32-bit data transfers between CPU and the dynamically reconfigurable circuits. The other implementation supports 64- bit transfers, but its effective use is more complicated and several restrictions must be taken into account. The work includes a performance comparison of the two designs on several simple tasks, including pattern matching, image processing and hashing.