Improving functional density through run-time constant propagation
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Revised5 report on the algorithmic language scheme
ACM SIGPLAN Notices
Derive: a tool that automatically reverse-engineers instruction encodings
DYNAMO '00 Proceedings of the ACM SIGPLAN workshop on Dynamic and adaptive compilation and optimization
JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Reverse-Engineering Instruction Encodings
Proceedings of the General Track: 2002 USENIX Annual Technical Conference
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Efficient Metacomputation Using Self-Reconfiguration
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
JHDL - An HDL for Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Dynamic FPGA routing for just-in-time FPGA compilation
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
From the bitstream to the netlist
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Hardware JIT compilation for off-the-shelf dynamically reconfigurable FPGAs
CC'08/ETAPS'08 Proceedings of the Joint European Conferences on Theory and Practice of Software 17th international conference on Compiler construction
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Just-In-Time (JIT) compilation is frequently used in software engineering to accelerate program execution. Parts of the code are translated to machine code at runtime to speedup their execution by exploiting local and dynamic information of the computation. Modern FPGAs manufactured by Xilinx allow partial and dynamic configuration. Such features make them eligible platforms for JIT hardware compilation. Nevertheless, this has not been achieved until now because the mapping between a bitstream and the programmable points inside these FPGAs is not documented. In this article, we propose a methodology to retrieve the relevant information in logarithmic time per bit by methodically using the tools distributed by Xilinx. We give a practical case study which details the analysis of a Virtex-II Pro FPGA bitstream. The mapping of CLBs, BRAMs, and multipliers has been fully determined. Thanks to this information, we have been able to prototype tools in the fields of reverse mapping FPGA bitstreams, low-level simulation, and custom place-and-route. Finally preliminary results demonstrate that a processor embedded in an FPGA can compile, place, and route arithmetic and logic expressions inside the FPGA within a few milliseconds.