Dynamically reconfigurable dataflow architecture for high-performance digital signal processing

Authors:
S. Voigt;M. Baesler;T. Teufel
Affiliations:
Hamburg University of Technology, Schwarzenbergstrasse 95, 21073 Hamburg, Germany;Hamburg University of Technology, Schwarzenbergstrasse 95, 21073 Hamburg, Germany;Hamburg University of Technology, Schwarzenbergstrasse 95, 21073 Hamburg, Germany
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2010

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Abstract

In this paper a dataflow architecture is introduced that maps efficiently onto multi-FPGA platforms and is composed of communication channels which can be dynamically adapted to the dataflow of the algorithm. The reconfiguration of the topology can be accomplished within a single clock cycle while DSP operations are in progress. Finally, the programmability and scalability of the proposed architecture is demonstrated by a high-performance parallel FFT implementation.