A dynamic reconfiguration run-time system
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A Lightweight Approach for Embedded Reconfiguration of FPGAs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Fault tolerant system design and SEU injection based testing
Microprocessors & Microsystems
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A popular research topic as of late has been dynamic partial FPGA (Field Programmable Gate Array) reconfiguration. This concept allows on-the-fly reconfiguration of digital systems where only parts of the circuit change, providing application acceleration and allowing static modules to continue processing unaffected by the dynamic elements. Design characteristics which benefit from this progressive approach include increased system flexibility, increased performance, and a reduction in circuit complexity. One characteristic receiving limited focus thus far has been the increased security that could result from these changing circuits. This benefit is innate to the design and makes reverse engineering of the system a much more ambitious task. In an effort to further enhance this passive security feature, a new partial reconfiguration technique has been proposed that changes connectivity between generic modules. This extended abstract introduces the method, model, and design flow for this dynamic partial FPGA reconfiguration technique and addresses the security implications of such a design.