FPGA clock management for low power applications (poster abstract)
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Clock-Gating in FPGAs: A Novel and Comparative Evaluation
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
An adaptive system-on-chip for network applications
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
How to efficiently implement dynamic circuit specialization systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Decentralized control for dynamically reconfigurable FPGA systems
Microprocessors & Microsystems
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Partial and dynamic online reconfiguration of Field Programmable Gate Arrays (FPGAs) is a promising approach to design high adaptive systems with lower power consumption, higher task specific performance, and even build-in fault tolerance. Different techniques and tool flows have been successfully developed. One of them, the two-dimensional partial reconfiguration, based on the Readback-Modify-Writeback method implemented on Xilinx Virtex devices, makes them ideally suited to be used as a hardware platform in future organic computing systems, where a highly adaptive hardware is necessary. In turn, decentralisation, the key property of an organic computing system, is in contradiction with the central nature of the FPGAs configuration port. Therefore, this paper presents an approach that connects the single ICAP port to a network on chip (NoC) to provide access for all clients of the network. Through this a virtual decentralisation of the ICAP is achieved. Further true 2-dimensional partial reconfiguration is raised to a higher level of abstraction through a lightweight Readback-Modify-Writeback hardware module with different configuration and addressing modes. Results show that configuration data as well as reconfiguration times could be significantly reduced.