High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Kernel scheduling in reconfigurable computing
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Reconfigurable computing: what, why, and implications for design automation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Priority Scheduling Versus Pre-Run-Time Scheduling
Real-Time Systems - Selected papers from IFAC/IFIP workshops on real-time programming
Scheduling for Embedded Real-Time Systems
IEEE Design & Test
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Online Scheduling for Block-Partitioned Reconfigurable Devices
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Lightweight Approach for Embedded Reconfiguration of FPGAs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
The Development of an Operating System for Reconfigurable Computing
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Physically-aware exploitation of component reuse in a partially reconfigurable architecture
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Colored Petri Net model with automatic parallelization on real-time multicore architectures
Journal of Systems Architecture: the EUROMICRO Journal
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Dynamic Reconfigurable Systems (DRS) offer a very interesting alternative for embedded digital systems design. Tasks scheduling within a reconfigurable environment allows the development of systems with better execution performance, chip area economy and lower power consumption. This paper describes an algorithm for design of dynamically reconfigurable systems where tasks scheduling have as prime objective the overall application performance speedup. The methodology includes the generation of an embedded controller supporting the scheduling process in a target architecture.