FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The design of an SRAM-based field-programmable gate array—part I: architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
How Much Logic Should Go in an FPGA Logic Block?
IEEE Design & Test
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
An Electrical Simulation Model for the Chalcogenide Phase-Change Memory Cell
MTDT '03 Proceedings of the 2003 International Workshop on Memory Technology, Design and Testing
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
The chimaera reconfigurable functional unit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of FPGA interconnect for multilevel metallization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
An RF circuit model for carbon nanotubes
IEEE Transactions on Nanotechnology
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Monolithically stackable hybrid FPGA
Proceedings of the Conference on Design, Automation and Test in Europe
SRAM-based NATURE: a dynamically reconfigurable FPGA based on 10T low-power SRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Rapid progress on nanodevices points to a promising direction for future circuit design. However, since nanofabrication techniques are not yet mature, implementation of nanocircuits, at least on a large scale, in the near future is infeasible. To ease fabrication and overcome the problem of high defect levels in nanotechnology, hybrid nano/CMOS reconfigurable architectures are attractive choices. Moreover, if the current photolithography fabrication process can be used to manufacture the hybrid chips, the benefits of nanotechnologies can be realized today. Traditional reconfigurable architectures can only support partial or coarse-grain runtime reconfiguration due to their limited on-chip storage and long off-chip reconfiguration latency. Recent progress on nano Random Access Memories (RAMs), such as carbon nanotube-based RAM (NRAM), Phase-Change Memory (PCM), magnetoresistive RAM (MRAM), etc., provides us with a chance to realize on-chip fine-grain runtime reconfiguration. These nano RAMs have good compatibility with the current fabrication process. By utilizing them in the hybrid design, we can take advantage of both CMOS and nanotechnology, and greatly improve the logic density, resource utilization, and performance of our design. In this article, we propose a high-performance reconfigurable architecture, called NATURE, that utilizes CMOS logic and nano RAMs. An automatic design flow for NATURE is presented in Part II of the article. In NATURE, the highly dense nonvolatile nano RAMs are distributed throughout the chip to allow large embedded on-chip configuration storage, which enables fast reading and hence supports fine-grain runtime reconfiguration and temporal logic folding of a circuit before being mapped to the architecture. Temporal logic folding can significantly increase the logic density of NATURE (by over an order of magnitude for large circuits) while remaining competitive in performance and power consumption. For ease of exposition, we use NRAMs to illustrate various concepts in this article due to the excellent properties of NRAMs. However, other nano RAMs can also be used instead. Experimental results based on NRAMs establish the efficacy of NATURE.