Compiler Optimizations for Adaptive EPIC Processors
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
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FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
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DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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This paper describes a customisable architecture and the associated tools for a prototype EPIC (Explicitly Parallel Instruction Computing) processor. Possible customisations include varying the number of registers and functional units, which are specified at compile-time. This facilitates the exploration of performance/area trade-off for different EPIC implementations. We describe the tools for this EPIC processor, which include a compiler and an assembler based on the Trimaran framework. Various pipelined EPIC designs have been implemented using Field Programmable Gate Arrays (FPGAs); the one with 4 ALUs at 41.8 MHz can run a DCT application 5 times faster than the StrongARM SA-110 processor at 100 MHz.