Memory size estimation for multimedia applications
Proceedings of the 6th international workshop on Hardware/software codesign
Memory modeling for system synthesis
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Global multimedia system design exploration using accurate memory organization feedback
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Extended design reuse trade-offs in hardware-software architecture mapping
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
System-level data format exploration for dynamically allocated data structures
Proceedings of the 37th Annual Design Automation Conference
Memory binding for performance optimization of control-flow intensive behaviors
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Flexible hardware acceleration for multimedia oriented microprocessors
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 14th international symposium on Systems synthesis
An integrated algorithm for memory allocation and assignment in high-level synthesis
Proceedings of the 39th annual Design Automation Conference
Color permutation: an iterative algorithm for memory packing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory Architectures for Embedded Systems-On-Chip
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
High-level synthesis of distributed logic-memory architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Energy efficient address assignment through minimized memory row switching
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power-efficient flexible processor architecture for embedded applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Memory allocation and mapping in high-level synthesis: an integrated approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Memory binding for performance optimization of control-flow intensive behavioral descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level synthesis using computation-unit integrated memories
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Transformation synthesis for data intensive applications to FPGAs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
EURASIP Journal on Embedded Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computationally efficient active rule detection method: Algorithm and architecture
Fuzzy Sets and Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Embedded memory binding in FPGAs
Proceedings of the 47th Design Automation Conference
MPack: global memory optimization for stream applications in high-level synthesis
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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This paper discusses the mapping of arrays in a behavior to memories in an implementation. We introduce a novel approach to the design of memory systems, which is based on a variety of array grouping techniques and dimensional transformations, and the binding of array groups to memory components with different dimensions, access times, and number of ports. The results of design actions are computed in terms of memory cost, the number of wires necessary to connect the memory to the data path, and the limit of performance imposed by the memory design on the implementation. Three different procedures can be used to find a suitable memory design. All three procedures are directed by a weighted and constrained system cost function, which enables the expression of the user's design priorities. Compared to related research efforts, our approach improves performance by as much as 19%, reduces memory cost as 40%, and decreases the number of wires required to connect the memory to the data path by up to 57%.