Mapping statechart models onto an FPGA-based ASIP architecture

  • Authors:
  • C. Veith;K. Buchenrieder;A. Pyttel

  • Affiliations:
  • Siemens AG, Corporate R&D, Otto-Hahn-Ring 6, 81730 Munich, Germany;Siemens AG, Corporate R&D, Otto-Hahn-Ring 6, 81730 Munich, Germany;Siemens AG, Corporate R&D, Otto-Hahn-Ring 6, 81730 Munich, Germany

  • Venue:
  • EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
  • Year:
  • 1996

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Abstract