Concurrent programming: principles and practice
Concurrent programming: principles and practice
ACM Computing Surveys (CSUR)
Integration of SDL and VHDL for high-level digital design
EURO-DAC '92 Proceedings of the conference on European design automation
A case study in computer-aided co-design of embedded controllers
Design Automation for Embedded Systems
Synthesis from mixed specifications
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Mapping statechart models onto an FPGA-based ASIP architecture
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Concepts and Notations for Concurrent Programming
ACM Computing Surveys (CSUR)
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Specification and Design of Embedded Hardware-Software Systems
IEEE Design & Test
Integrating SDL and VHDL for System-Level Hardware Design
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Specification Languages for Communication Protocols
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Model Refinement for Hardware-Software Codesign
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Co-Design Methodology Based on Formal Specification and High-level Estimation
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
VHDL system-level specification and partitioning in a hardware/software co-synthesis environment
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Translating system specifications to VHDL
EURO-DAC '91 Proceedings of the conference on European design automation
SpecCharts: a VHDL front-end for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An FPGA based soft multiprocessor for DNS/DNSSEC authoritative server
Microprocessors & Microsystems
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The aim of this paper is to present an approach that allows the generation of VHDL from system level specifications in SDL. Our approach overcomes the main known problem encountered by previous work, which is the communication between different processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by the use of an intermediate form that supports a powerful communication model which enables the representation in a synthesis oriented manner of most communication schemes. This intermediate form allows the refinement of the system in order to obtain the desired solution. The main refinement step, called communication synthesis, is aimed at fixing the protocol and the interface used by the different processes to communicate. The refined specification is translated into VHDL for synthesis using existing CAD tools. We illustrate the feasibility of our approach through two SDL to VHDL translation examples.