OO-VHDL: Object-Oriented Extensions to VHDL

• Authors: Sowmitri Swamy;Arthur Molin;Burt Covnot
• Venue: Computer
• Year: 1995

Object-oriented approaches to software development have gained widespread acceptance as a way to manage design complexity and increase software reuse. These same needs are driving efforts to add object-oriented capabilities to hardware description languages (HDLs). VHDL (VHSIC hardware description language) was developed under the auspices of the US Department of Defense's Very High Speed Integrated Circuits (VHSIC) program in the 1980s. The current DoD effort, called RASSP (Rapid Prototyping of Application-Specific Signal Processors), is an ambitious undertaking to reduce, by a factor of four, the cost and time needed to design, upgrade, and replace embedded digital signal processors. To reach this goal, VHDL and its extensions must be used throughout the design process and at all levels from system to gate. VHDL has a number of constructs that have direct correlations in digital hardware; the most important are the component, which encapsulates a "black box" view of a piece of hardware, and the signal, which models a wire. Such constructs make VHDL suitable for developing detailed low-level models, but they make it difficult to write abstract high-level models. For system-level descriptions of behavior, a computation model more in line with software systems seems suitable. In this model, individual modules are reactive; that is, they respond only to a command/instruction or stimulus, communication is point-to-point, and the individual addressability of modules allows for temporary implicit communication pathways without the specificity of ports and interconnections. OO-VHDL, the object-oriented extension language of VHDL described in this article, supports both the VHDL computation model and the reactive computation model. The authors have implemented a preprocessor that translates OO-VHDL to VHDL and a debugging tool that maps VHDL statements into the OO-VHDL statements from which they were derived. Thus, modelers will be able to use OO-VHDL in current VHDL environments.