Object oriented hardware synthesis and verification

Authors:
T. Kuhn;T. Oppold;C. Schulz-Key;M. Winterholer;W. Rosenstiel;M. Edwards;Y. Kashai
Affiliations:
Univ. of Tuebingen, Tuebingen, Germany;Univ. of Tuebingen, Tuebingen, Germany;Univ. of Tuebingen, Tuebingen, Germany;Univ. of Tuebingen, Tuebingen, Germany;Univ. of Tuebingen, Tuebingen, Germany;Cisco Systems, Inc., RTP, NC;Verisity Design, Inc., Mountain View, CA
Venue:
Proceedings of the 14th international symposium on Systems synthesis
Year:
2001

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Abstract

The synthesis of hardware from object oriented specifications is presented. Our approach utilizes the e language that has been proven to be highly efficient for the verification of hardware. The e language is similar to Java and provides additional constructs for specification and verification of hardware. We describe an automated design flow for the synthesis of object oriented descriptions that tightly integrates simulation based verification. The usability of our approach is demonstrated by real-world examples.