Communicating sequential processes
Communicating sequential processes
Concurrency and reusability: from sequential to parallel
Journal of Object-Oriented Programming
Real-time object-oriented modeling
Real-time object-oriented modeling
Specification and design of embedded systems
Specification and design of embedded systems
Inheritance concept for signals in object-oriented extensions to VHDL
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Object oriented extensions to VHDL, the LaMI proposal
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
SUAVE: Painless Extension For An Object-Oriented VHDL
VIUF '97 Proceedings of the 1997 VHDL International User's Forum (VIUF '97)
Object-oriented reuse methodology for VHDL
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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When defining an object-oriented extension to VHDL, the necessary message passing is one of the most complex issues and has a large impact on the whole language. This paper identifies the requirements for message passing suited to model hardware and classifies different approaches. To allow abstract communication and reuse of protocols on system level, a new, flexible message passing mechanism proposed for Objective VHDL will be introduced.