Statecharts: A visual formalism for complex systems
Science of Computer Programming
Structured analysis and VHDL in embedded ASIC design and verification
EURO-DAC '90 Proceedings of the conference on European design automation
Integration of SDL and VHDL for high-level digital design
EURO-DAC '92 Proceedings of the conference on European design automation
Using VHDL for simulation of SDL specifications
EURO-DAC '92 Proceedings of the conference on European design automation
Cosimulation of real-time control systems
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
VHDL-based communication and synchronization synthesis
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Rapid prototyping of microprocessor-based systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
VHDL generation from SDL specifications
Readings in hardware/software co-design
Using VHDL for High-Level, Mixed-Mode System Simulation
IEEE Design & Test
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IEEE Design & Test
Computer-Aided Hardware-Software Codesign
IEEE Micro
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Languages based on hierarchical and concurrent state diagrams are powerful in specifying system level designs. Simulating such languages can be simplified by translating to a simulation language such as VHDL and then using available simulators. This paper describes system level abstractions commonly found in specification languages and presents semantic preserving VHDL implementations.