Structured analysis and VHDL in embedded ASIC design and verification

Authors:
Tuomo Tikkanen;Timo Lappänen;Jorma Kivelä
Affiliations:
Technical Research Centre of Finland, Electronics laboratory, 1OULU, FINLAND;University of Oulu, Electronics Laboratory, OULU, Finland;University of Oulu, Electronics Laboratory, OULU, Finland
Venue:
EURO-DAC '90 Proceedings of the conference on European design automation
Year:
1990

Citing 3
Cited 3

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Integration of SDL and VHDL for high-level digital design

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Translating system specifications to VHDL

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Abstract

With current VLSI technology it has become possible to integrate complex systems in a single chip. Therefore much more efficient design and verification methods are needed especially at system level. We are using Real-Time Structured Analysis / Structured Design in logical behaviour specification and design of systems. We have developed automatic transformation from this graphical analysis and specification method to VHDL-Hardware Description Language. The resulting code can be simulated and so the behaviour of system can be verified at an early design phase. This paper presents the transformation principles and also describes the whole design process of ASICs.