Integration of SDL and VHDL for high-level digital design

Static scheduling of synchronous data flow programs for digital signal processing

IEEE Transactions on Computers

What's in a timing discipline? Considerations in the specification and synthesis of systems with interacting asynchronous and synchronous components

Proceedings of the Mathematical Sciences Institute workshop on Hardware specification, verification and synthesis: mathematical aspects

SDL-VHDL integration

Method integration

Consistency in Dataflow Graphs

IEEE Transactions on Parallel and Distributed Systems

Structured analysis and VHDL in embedded ASIC design and verification

EURO-DAC '90 Proceedings of the conference on European design automation

Translating system specifications to VHDL

EURO-DAC '91 Proceedings of the conference on European design automation