Phase coupling and constant generation in an optimizing microcode compiler
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
A retargetable compiler for a high-level microprogramming language
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
Global methods in the flow graph approach to retargetable microcode generation
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
Methods of compacting microprograms
Methods of compacting microprograms
Local code generation and compaction in optimizing microcode compilers
Local code generation and compaction in optimizing microcode compilers
Verification of hardware descriptions by retargetable code generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Generating compilers for generated datapaths
EURO-DAC '94 Proceedings of the conference on European design automation
Time-constrained code compaction for DSPs
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Using compilers for heterogeneous system design
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Instruction set definition and instruction selection for ASIPs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Retargetable assembly code generation by bootstrapping
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
A processor desription language supporting retargetable multi-pipeline DSP program development tools
Proceedings of the 11th international symposium on System synthesis
PROPAN: A Retargetable System for Postpass Optimisations and Analyses
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Description and Simulation of Microprocessor Instruction Sets Using ASMs
ASM '00 Proceedings of the International Workshop on Abstract State Machines, Theory and Applications
Instruction-Set Modeling for ASIP Code Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Matching system and component behaviour in MIMOLA synthesis tools
EURO-DAC '90 Proceedings of the conference on European design automation
TDL: a hardware description language for retargetable postpass optimizations and analyses
Proceedings of the 2nd international conference on Generative programming and component engineering
Processor Description Languages
Processor Description Languages
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This paper describes a retargetable compiler, which is able to compile programs into the machine code of a specified hardware (target). The target is described at register-transfer structure level by module specifications and netlists. The program can be defined at several levels of abstraction, spanning the range from algorithmic description (e.g. PASCAL) down to RT-level behavioural description. If the program is the complete target's behavioural specification the compiler can be used to verify the structural against this behavioural description.