ADSP-2100 Family user's manual
ADSP-2100 Family user's manual
A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An ASIP instruction set optimization algorithm with functional module sharing constraint
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Code generation for core processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
A Graph Based Processor Model for Retargetable Code Generation
EDTC '96 Proceedings of the 1996 European conference on Design and Test
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This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.