Verification of hardware descriptions by retargetable code generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Code generation using tree matching and dynamic programming
ACM Transactions on Programming Languages and Systems (TOPLAS)
Conflict modelling and instruction scheduling in code generation for in-house DSP cores
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal code generation for embedded memory non-homogeneous register architectures
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Time-constrained code compaction for DSPs
ISSS '95 Proceedings of the 8th international symposium on System synthesis
A BDD-based frontend for retargetable compilers
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Synthesis of application specific instructions for embedded DSP software
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Synthesis of Application Specific Instructions for Embedded DSP Software
IEEE Transactions on Computers
Simultaneous reference allocation in code generation for dual data memory bank ASIPs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Code selection for media processors with SIMD instructions
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Graph-based code selection techniques for embedded processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Designing domain-specific processors
Proceedings of the ninth international symposium on Hardware/software codesign
Static resource models of instruction sets
Proceedings of the 14th international symposium on Systems synthesis
Embedded software in real-time signal processing systems: design technologies
Readings in hardware/software co-design
Readings in hardware/software co-design
Static resource models for code-size efficient embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions
IEEE Transactions on Computers
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration
IEEE Transactions on Computers
Scalable subgraph mapping for acyclic computation accelerators
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping
Proceedings of the International Symposium on Code Generation and Optimization
A code-generator generator for multi-output instructions
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Preprocessing strategy for effective modulo scheduling on multi-issue digital signal processors
CC'07 Proceedings of the 16th international conference on Compiler construction
Implementing dynamic implied addressing mode for multi-output instructions
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Compiling for automatically generated instruction set extensions
Proceedings of the Tenth International Symposium on Code Generation and Optimization
| Hi-index | 0.01 |