Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simple on-the-fly automatic verification of linear temporal logic
Proceedings of the Fifteenth IFIP WG6.1 International Symposium on Protocol Specification, Testing and Verification XV
Improved Automata Generation for Linear Temporal Logic
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Probabilistic Verification of Discrete Event Systems Using Acceptance Sampling
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
A Bayesian Approach to Model Checking Biological Systems
CMSB '09 Proceedings of the 7th International Conference on Computational Methods in Systems Biology
Bayesian statistical model checking with application to Simulink/Stateflow verification
Proceedings of the 13th ACM international conference on Hybrid systems: computation and control
| Hi-index | 0.00 |
Statistical model checking is a method to analyze systems where values of variables may have some uncertainty or variations. It can be used to check whether some desired properties are satisfied with specified probability under such uncertainty. In statistical model checking, the system needs to be repeatedly simulated and checked for properties represented in Bounded Linear Temporal Logic (BLTL). The property checking takes a long time if a property includes many variables and/or if the analysis is performed for long sequences. In this paper, we propose a hardware implementation of BLTL property checkers to accelerate the property checking process in statistical model checking. Through the experimental results on Tsunami simulation with variations of earthquake parameters, we show that the total execution time of statistical model checking can be shorten by more than 30 times compared to a software implementation, by implementing our proposed BLTL property checkers on FPGA.