Testability analysis and ATPG on behavioral RT-level VHDL

Authors:
Fulvio CORNO;Paolo PRINETTO;Matteo SONZA REORDA
Affiliations:
-;-;-
Venue:
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Year:
1997

Citing 3
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Abstract

This paper proposes an environment to address TestabilityAnalysis and Test Pattern Generation on VHDLdescriptions at the RT-level. The proposed approach,based on a suitable fault model and an ATPG algorithm,is experimentally shown to provide a good estimateof the final gate-level fault coverage, and to givetest patterns with excellent fault coverage properties.The approach, being based on an abstract representation,is particularly suited for large circuits, where gate-levelATPGs are often inefficient.