Embedded tutorial: essential issues for IP reuse
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
UML Distilled: A Brief Guide to the Standard Object Modeling Language
UML Distilled: A Brief Guide to the Standard Object Modeling Language
ISESE '03 Proceedings of the 2003 International Symposium on Empirical Software Engineering
Systemic Embedded Software Generation from SystemC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Model-Driven SoC Design via Executable UML to SystemC
RTSS '04 Proceedings of the 25th IEEE International Real-Time Systems Symposium
A SoC Design Methodology Involving a UML 2.0 Profile for SystemC
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Modeling SystemC design in UML and automatic code generation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A smooth refinement flow for co-designing HW and SW threads
Proceedings of the conference on Design, automation and test in Europe
A Model-Driven Development Approach to Mapping UML State Diagrams to Synthesizable VHDL
IEEE Transactions on Computers
Foundations of a compositional interchange format for hybrid systems
HSCC'07 Proceedings of the 10th international conference on Hybrid systems: computation and control
Abstraction of RTL IPs into embedded software
Proceedings of the 47th Design Automation Conference
The SATURN Approach to SysML-Based HW/SW Codesign
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Design and verification of systemc transaction-level models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HIFsuite: tools for HDL code conversion and manipulation
EURASIP Journal on Embedded Systems
Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions
IEEE Transactions on Computers
Transformation of SysML Structure Diagrams to VHDL-AMS
DMEMS '12 Proceedings of the 2012 Second Workshop on Design, Control and Software Implementation for Distributed MEMS
UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration
IEEE Transactions on Computers
On the Reuse of RTL IPs for SysML Model Generation
MTV '12 Proceedings of the 2012 13th International Workshop on Microprocessor Test and Verification
FPGA Synthesis of VHDL OFDM System
Wireless Personal Communications: An International Journal
| Hi-index | 0.00 |
The paper proposes an integrated methodology to abstract already existing heterogeneous IPs into SysML behavioral equivalent models. This approach aims at integrating the abstracted components with partially specified platforms at SysML level and verifying their integration. During the abstraction flow, the level of details can be chosen according to the needs of the designer. They are related to communication and synchronization protocols, hierarchical structure, and data types of the abstracted IPs and the details about continuous flows to be abstracted in SysML. Therefore, the generated SysML models can preserve information about structure in combination with the functional description for continuous and discrete behaviors and, thus, they can be synthesized into C++ or modeling tools like Matlab Simulink. This can be used to verify the integration of the so generated models exploiting simulation based techniques. The main benefit of the proposed methodology is relieving designers from the modeling time and error risks especially for those designs in which the SysML model of the architecture is particularly structured and detailed. The approach has been fully integrated and extended to support also components with analogic behaviors. The proposed framework has been applied positively to different benchmarks in order to be validated. Three case studies are presented in order to better understand the approach applicability and effectiveness.