On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation
Journal of Electronic Testing: Theory and Applications
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In this paper, we propose an approach to translate the Sys ML language to VHDL-AMS code. This approach is the first step to the generation of the VHDL-AMS code from the structural diagrams Sys ML. In this step, we address the Block Definition Diagram and the Internal Block Diagram. The translation uses Model Driven Engineer (MDE) methods as the transformation of model to another model (M2M) with ATL Atlas Transformation Language and the code generation from models (M2T) using Xpand. We provide the translation rules between the two elements. Implementation and methodology are illustrated on a micro-system case study: the Smart surface system.