On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation
Journal of Electronic Testing: Theory and Applications
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The main obstacle for the wide acceptance of UML and SysML in the design of electronic systems is due to a major gap in the design flow between UML-based modeling and SystemC-based verification. To overcome this gap, we present an approach developed in the SATURN project which introduces UML profiles for the co-modeling of SystemC and C with code generation support in the context of ARTiSAN Studio®. We finally discuss the evaluation of the approach by two case studies.