On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.98 |
With the continuing rise in the complexity of embedded systems, there is an emerging need for a higher level modelling environment that facilitates efficient handling of this complexity. The aim here is to produce such a high level environment using Model Driven Development (MDD) techniques that maps a high level abstract description of an electronic embedded system into its low level implementation details. The Unified Modelling Language (UML) is a high level graphical based language that is broad enough in scope to model embedded systems hardware circuits. The authors have developed a framework for deriving Very High Speed Integrated Circuits Hardware Description Language (VHDL) code from UML state diagrams and defined a set of rules that enable automated generation of synthesisable VHDL code from UML specifications using MDD techniques. By adopting the techniques and tools described in this paper the design and implementation of complex state-based systems is greatly simplified.