Multi-level fault modeling for transaction-level specifications
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Abstraction of RTL IPs into embedded software
Proceedings of the 47th Design Automation Conference
HIFsuite: tools for HDL code conversion and manipulation
EURASIP Journal on Embedded Systems
Simulation-based equivalence checking between SystemC models at different levels of abstraction
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Automated formal verification of processors based on architectural models
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Equivalence checking between function block diagrams and C programs using HW-CBMC
SAFECOMP'11 Proceedings of the 30th international conference on Computer safety, reliability, and security
Automatic RTL Test Generation from SystemC TLM Specifications
ACM Transactions on Embedded Computing Systems (TECS)
FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction
Journal of Electronic Testing: Theory and Applications
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The always increasing complexity of digital system is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at different abstraction levels. The design implementation starts from a TLM high-level description and, following a topdown approach, it is refined towards a corresponding RTL model. However, the bottom-up approach is also adopted in the design flow when already existing RTL IPs are abstracted to be reused into the TLM system. In this context, proving the equivalence between a model and its refined or abstracted version is still an open problem. In fact, traditional equivalence definitions and formal equivalence checking methodologies presented in the literature cannot be applied due to the very different internal characteristics of the models, including structure organization and timing. Targeting this topic, the paper presents a formal definition of equivalence based on events, and then, it shows how such a definition can be used for proving the equivalence in the RTL vs. TLM context, without requiring timing or structural similarities between the modules to be compared. Finally, the paper presents a practical use of the proposed theory, by proving the correctness of a methodology that automatically abstracts RTL IPs towards TLM implementations.