Symbolic Model Checking
The verifying compiler: A grand challenge for computing research
Journal of the ACM (JACM)
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Hardware verification using ANSI-C programs as a reference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Towards Equivalence Checking Between TLM and RTL Models
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
| Hi-index | 0.00 |
Controllers in safety critical systems such as nuclear power plants often use Function Block Diagrams (FBDs) to design embedded software. The design program are translated into programming languages such as C to compile it into machine code for particular target hardware. It is required to verify equivalence between the design and the implementation, because the implemented program should have same behavior with the design. This paper introduces a technique about verifying equivalence between a design written in FBDs and its implementation written in C language using HW-CBMC. To demonstrate the effectiveness of our proposal, as a case study, we used one of 18 shutdown logics in a prototype of Advanced Power Reactor's (APR-1400) Reactor Protection System (RPS) in Korea. Our approach is effective to check equivalence between FBDs and ANSI-C programs if the automatically generated Verilog program is translated into appropreate one of the HW-CBMC.