DAC '98 Proceedings of the 35th annual Design Automation Conference
Validating the intel pentium 4 microprocessor
Proceedings of the 38th annual Design Automation Conference
Coverage directed test generation for functional verification using bayesian networks
Proceedings of the 40th annual Design Automation Conference
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Opportunities and Challenges in Building Silicon Products in 65nm and Beyond
Proceedings of the conference on Design, automation and test in Europe - Volume 1
StressTest: an automatic approach to test generation via activity monitors
Proceedings of the 42nd annual Design Automation Conference
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems
IBM Journal of Research and Development
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The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This trend is accelerated with the advent of highly integrated system-on-a-chip (SoC) designs, which feature multiple complex subcomponents connected by simultaneously active interfaces.In this paper, we introduce a closed-loop feedback technique targeting the verification of multiple components connected by parallel interfaces. We utilize an environment with hierarchical Markov models, where top-level submodels specify overarching simulation goals of the system, while lower-level submodels specify the detailed component-level input generation. Test accuracy is improved through the use of depth-driven random test generation. The approach allows users to specify correctness properties and key activity nodes in the design to be exercises. We examine three non-trivial designs, two microprocessors and a chip multiprocessor router switch, and we demonstrate that our technique finds many more bugs than constrained-random test generation technique and reduces the simulation effort in half, compared to previous Markov-model based solutions.