Validation coverage analysis for complex digital designs
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
A validation fault model for timing-induced functional errors
Proceedings of the IEEE International Test Conference 2001
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
OCCOM-efficient computation of observability-based code coverage metrics for functional verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test generation for clock-domain crossing faults in integrated circuits
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Multiple asynchronous clock domains have been increasingly employed in System-on-Chip (SoC) designs for different I/O interfaces. Functional validation is one of the most expensive tasks in the SoC design process. Simulation on register transfer level (RTL) is still the most widely used method. It is important to quantitatively measure the validation confidence and progress for clock domain crossing (CDC) designs. In this paper, we propose an efficient method for definition of CDC coverage, which can be used in RTL simulation for a multi-clock domain SoC design. First, we develop a CDC fault model to present the actual effect of metastability. Second, we use a temporal data flow graph (TDFG) to propagate the CDC faults to observable variables. Finally, CDC coverage is defined based on the CDC faults and their observability. Our experiments on a commercial IP demonstrate that this method is useful to find CDC errors early in the design cycles.