The case for a configure-and-execute paradigm
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Interface and cache power exploration for core-based embedded system design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A hybrid approach for core-based system-level power modeling
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Parameterised system design based on genetic algorithms
Proceedings of the ninth international symposium on Hardware/software codesign
A design framework to efficiently explore energy-delay tradeoffs
Proceedings of the ninth international symposium on Hardware/software codesign
Multiple Objective Optimization with Vector Evaluated Genetic Algorithms
Proceedings of the 1st International Conference on Genetic Algorithms
Multiobjective Evolutionary Algorithms: Analyzing the State-of-the-Art
Evolutionary Computation
Comparison of Multiobjective Evolutionary Algorithms: Empirical Results
Evolutionary Computation
Multiobjective evolutionary algorithms: a comparative case studyand the strength Pareto approach
IEEE Transactions on Evolutionary Computation
Safe integration of parameterized IP
Integration, the VLSI Journal - Special issue: IP and design reuse
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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The paper presents two new approaches to multi-objective design space exploration for parametric VLSI systems. Both considerably reduce the number of situlations needed to determine the Pareto-optical set as compared with an exhaustive approach.The first uses sensitivity analysis while the second uses evolutionary computing techniques. Application to a highly parametric system-on-a-chip for digital camera applications shows the validity of the methodologies presented in terms of both accuracy of results and efficiency, measured as the number of simulations needed to determine the power/execution-time trade-off front.