Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Term rewriting and all that
Verifying out-of-order executions
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Formal Verification of Out-of-Order Execution Using Incremental Flushing
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verifying Advanced Microarchitectures that Support Speculation and Exceptions
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
A reflective functional language for hardware design and theorem proving
Journal of Functional Programming
A complete compositional reasoning framework for the efficient verification of pipelined machines
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Tool Building Requirements for an API to First-Order Solvers
Electronic Notes in Theoretical Computer Science (ENTCS)
Getting Formal Verification into Design Flow
FM '08 Proceedings of the 15th international symposium on Formal Methods
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We present a method for pipeline verification using SMT solvers. It is based on a non-deterministic ''mother pipeline'' machine (MOP) that abstracts the instruction set architecture (ISA). The MOP vs. ISA correctness theorem splits naturally into a large number of simple subgoals. This theorem reduces proving the correctness of a given pipelined implementation of the ISA to verifying that each of its transitions can be modeled as a sequence of MOP state transitions.