Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
Microprocessor design verification
Journal of Automated Reasoning
Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Verifying parameterized networks
ACM Transactions on Programming Languages and Systems (TOPLAS)
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analysis of composition complexity and how to obtain smaller canonical graphs
Proceedings of the 37th Annual Design Automation Conference
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Symbolic Model Checking
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Formalizing Inductive Proofs of Network Algorithms
ACSC '95 Proceedings of the 1995 Asian Computing Science Conference on Algorithms, Concurrency and Knowledge
Experiments in Theorem Proving and Model Checking for Protocol Verification
FME '96 Proceedings of the Third International Symposium of Formal Methods Europe on Industrial Benefit and Advances in Formal Methods
Processor Verification with Precise Exeptions and Speculative Execution
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Verification of the Futurebus+ Cache Coherence Protocol
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Towards a formal theory of on chip communications in the ACL2 logic
ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
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We present a generic network on chip model (named GeNoC) intended to serve as a reference for the design and the validation of high level specifications of communication virtual modules. The definition of the model relies on three independent groups of constrained functions: routing and topology, scheduling, interfaces. The model identifies the sufficient constraints that these functions must satisfy in order to prove the correctness of GeNoC. Hence, one can concentrate his efforts on the design and the verification of one group. As long as the constraints are satisfied the overall system correctness is still valid. We show some concrete instances of GeNoC. One of them is a state-of-the-art network taken from industry.