On the architecture of system verification environments
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Realistic worst-case execution time analysis in the context of pervasive system verification
Program analysis and compilation, theory and practice
Model checking the FlexRay physical layer protocol
FMICS'10 Proceedings of the 15th international conference on Formal methods for industrial critical systems
| Hi-index | 0.00 |
We present a formal model of the bit transmission between registers with arbitrary clock periods. Our model considers precise timing parameters, as well as metastability. We formally define the behavior of registers over time. From that definition, we prove, under certain conditions, that data are properly transmitted. We discuss how to incorporate the model in a purely digital model. The hypotheses of our main theorem define conditions that must be satisfied by the purely digital part of the system to preserve correctness.