Putting it all together – Formal verification of the VAMP

Authors:
Sven Beyer;Christian Jacobi;Daniel Kröning;Dirk Leinenbach;Wolfgang J. Paul
Affiliations:
OneSpin Solutions GmbH, 80339, Munich, Germany;IBM Deutschland Entwicklung GmbH, 71032, Böblingen, Germany;ETH Zürich, Computer Systems Institute, 71032, Zürich, Switzerland;Saarland University, Computer Science Department, 66123, Saarbrücken, Germany;Saarland University, Computer Science Department, 66123, Saarbrücken, Germany
Venue:
International Journal on Software Tools for Technology Transfer (STTT) - A View from Formal Methods 2003 (pp 301-354); Special Section on Recent Advances in Hardware Verification (pp 355-447)
Year:
2006

Citing 0
Cited 25

An approach to the pervasive formal specification and verification of an automotive system: status report

Proceedings of the 10th international workshop on Formal methods for industrial critical systems
Towards the Formal Verification of a C0 Compiler: Code Generation and Implementation Correctnes

SEFM '05 Proceedings of the Third IEEE International Conference on Software Engineering and Formal Methods
Pervasive Compiler Verification -- From Verified Programs to Verified Systems

Electronic Notes in Theoretical Computer Science (ENTCS)
A Formal Model of Memory Peculiarities for the Verification of Low-Level Operating-System Code

Electronic Notes in Theoretical Computer Science (ENTCS)
CVM -- A Verified Framework for Microkernel Programmers

Electronic Notes in Theoretical Computer Science (ENTCS)
Correct Microkernel Primitives

Electronic Notes in Theoretical Computer Science (ENTCS)
A Verification Approach for System-Level Concurrent Programs

VSTTE '08 Proceedings of the 2nd international conference on Verified Software: Theories, Tools, Experiments
Verified Process-Context Switch for C-Programmed Kernels

VSTTE '08 Proceedings of the 2nd international conference on Verified Software: Theories, Tools, Experiments
Balancing the Load

Journal of Automated Reasoning
Proving Fairness and Implementation Correctness of a Microkernel Scheduler

Journal of Automated Reasoning
Formal Memory Models for the Verification of Low-Level Operating-System Code

Journal of Automated Reasoning
Formal Verification of Gate-Level Computer Systems

CSR '09 Proceedings of the Fourth International Computer Science Symposium in Russia on Computer Science - Theory and Applications
A Formally Verified Compiler Back-end

Journal of Automated Reasoning
HOL-Boogie--An Interactive Prover-Backend for the Verifying C Compiler

Journal of Automated Reasoning
Formal pervasive verification of a paging mechanism

TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Pervasive verification of an OS microkernel: inline assembly, memory consumption, concurrent devices

VSTTE'10 Proceedings of the Third international conference on Verified software: theories, tools, experiments
UML for software safety and certification: model-based development of safety-critical software-intensive systems

MBEERTS'07 Proceedings of the 2007 International Dagstuhl conference on Model-based engineering of embedded real-time systems
Lyrebird: assigning meanings to machines

SSV'10 Proceedings of the 5th international conference on Systems software verification
From operating-system correctness to pervasively verified applications

IFM'10 Proceedings of the 8th international conference on Integrated formal methods
Provable Security: how feasible is it?

HotOS'13 Proceedings of the 13th USENIX conference on Hot topics in operating systems
Automated formal verification of processors based on architectural models

Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
System description: Combination of Isabelle/HOL with automatic tools

FroCoS'05 Proceedings of the 5th international conference on Frontiers of Combining Systems
Improving interrupt response time in a verifiable protected microkernel

Proceedings of the 7th ACM european conference on Computer Systems
FPGA paranoia: testing numerical properties of FPGA floating point IP-Cores

ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Formal verification of hardware synthesis

CAV'13 Proceedings of the 25th international conference on Computer Aided Verification

Quantified Score

Hi-index	0.00

Visualization

Abstract

In the verified architecture microprocessor (VAMP) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA.