Formal pervasive verification of a paging mechanism

  • Authors:
  • Eyad Alkassar;Norbert Schirmer;Artem Starostin

  • Affiliations:
  • Computer Science Department, Saarland University;Computer Science Department, Saarland University;Computer Science Department, Saarland University

  • Venue:
  • TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
  • Year:
  • 2008

Quantified Score

Hi-index 0.02

Visualization

Abstract

Memory virtualization by means of demand paging is a crucial component of every modern operating system. The formal verification is challenging since reasoning about the page fault handler has to cover two concurrent computational sources: the processor and the hard disk. We accurately model the interleaved executions of devices and the page fault handler, which is written in a high-level programming language with inline assembler portions. We describe how to combine results from sequential Hoare logic style reasoning about the page fault handler on the low-level concurrent machine model. To the best of our knowledge this is the first example of pervasive formal verification of software communicating with devices.