Performance analysis of concurrent systems with early evaluation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Synchronous elastic circuits with early evaluation and token counterflow
Proceedings of the 44th annual Design Automation Conference
Using functional independence conditions to optimize the performance of latency-insensitive systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Transactions on Petri Nets and Other Models of Concurrency I
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Retiming and recycling for elastic systems with early evaluation
Proceedings of the 46th Annual Design Automation Conference
Speculation in elastic systems
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Basic qualitative properties of Petri nets with multi-guarded transitions
ACC'09 Proceedings of the 2009 conference on American Control Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Data-dependent completion time is a well-known advantage of self-timed circuits, one that allows them to operate at average rather than worst-case execution rates. A technique called early evaluation (EE) that extends this advantage by allowing self-timed modules to produce results before all of their inputs have arrived is described here. The technique can be applied to any combinational function and is integrated into the phased logic (PL) design methodology that accepts synchronous design entry and produces delay-insensitive self-timed circuits. We describe an algorithm that ensures that the resulting delay-insensitive circuits are safe, and develop a generalized method for inserting EE gates into any PL netlist. We give performance results for several benchmark circuits, including a five-stage pipelined CPU and a microprogrammed floating-point unit. Comparisons are made among clocked circuits, PL circuits, and PL circuits with EE. Simulation results show a clear performance benefit for PL circuits that use EE.