Synchronous programming with events and relations: the SIGNAL language and its semantics
Science of Computer Programming
Implementation of the data-flow synchronous language SIGNAL
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
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A Protocol for Loosely Time-Triggered Architectures
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Polychrony for Formal Refinement-Checking in a System-Level Design Methodology
ACSD '03 Proceedings of the Third International Conference on Application of Concurrency to System Design
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verification of GALS Systems by Combining Synchronous Languages and Process Calculi
Proceedings of the 16th International SPIN Workshop on Model Checking Software
On the formal verification of systems of synchronous software components
SAFECOMP'12 Proceedings of the 31st international conference on Computer Safety, Reliability, and Security
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Starting with modules described in Signal synchronous programming language, we present an approach to verification of GALS systems. Since asynchronous parts of a GALS system can not be described in Signal, we use a mixture of synchronous descriptions in Signal and asynchronous descriptions in Promela. Promela is the input language to the SPIN asynchronous model checker. This allows us to achieve globally asynchronous composition (Promela) of locally synchronous components (Signal). Here we present three key results: first, we present a translation from Signal modules to Promela processes and prove their equivalence. Second, we present a technique to abstract a communication bus designed for GALS, the Loosely Time-Triggered Architecture (LTTA) bus, to a finite FIFO channel. The benefit of this abstraction is improved scalability for model checking larger specifications using SPIN. Third, we prove the trace equivalence of the model of the GALS system in Promela and a hardware implementation of it. This allows the verification of GALS systems based on the Promela model. We then use our technique to verify a central locking system for automobiles built on a GALS architecture using the LTTA.