The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Performance of data networks with random links
Mathematics and Computers in Simulation
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Cycle-Accurate Energy Measurement and Characterization of FPGAs
Analog Integrated Circuits and Signal Processing
Application-specific network-on-chip architecture customization via long-range link insertion
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Proceedings of the 41st annual Design Automation Conference
Topology/floorplan/pipeline co-design of cascaded crossbar bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An analytical network performance model for SIMD processor CSX600 interconnects
Journal of Systems Architecture: the EUROMICRO Journal
"It's a small world after all": noc performance optimization via long-range link insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Systems Architecture: the EUROMICRO Journal
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Network-on-Chip (NoC)-based communication represents a promising solution to complex on-chip communication problems. Due to their regular structure, mesh-like NoC architectures have become very popular recently. However, they have poor topological properties such as long inter-node distances. In this paper, we address this very issue and explore the potential of partial NoC customization to improve both static and dynamic properties of the network significantly, while minimally affecting its regularity. Precise energy measurements on an FPGA prototype show that the improvement in network properties is achieved without a significant penalty in area and communication energy consumption.