SuperENC: MPEG-2 Video Encoder Chip
IEEE Micro
Performance of H.26L Video Encoder on General-Purpose Processor
Journal of VLSI Signal Processing Systems
Hardware-software co-implementation of a H.263 video codec
IEEE Transactions on Consumer Electronics
Multicore system-on-chip architecture for MPEG-4 streaming video
IEEE Transactions on Circuits and Systems for Video Technology
A unified systolic architecture for combined inter and intra predictions in H.264/AVC decoder
Proceedings of the 2006 international conference on Wireless communications and mobile computing
A multiple-window video embedding transcoder based on H.264/AVC standard
EURASIP Journal on Advances in Signal Processing
Trend and Challenge on System-on-a-Chip Designs
Journal of Signal Processing Systems
A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters
Journal of Signal Processing Systems
Development of a high-level simulation approach and its application to multicore video decoding
IEEE Transactions on Circuits and Systems for Video Technology
A Low-overhead Scheduling Methodology for Fine-grained Acceleration of Signal Processing Systems
Journal of Signal Processing Systems
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We present a baseline MPEG-4 Advanced Video Coding (AVC) decoder based on the methodology of joint optimization of software and hardware. The software is first optimized with algorithm improvements for frame buffer management, boundary padding, content-aware inverse transform and context-based entropy decoding. The overall decoding throughput is further enhanced by pipelining the software and the dedicated hardware at macroblock level. The decoder is partitioned into the software and hardware modules according to the target frame rate and complexity profiles. The hardware acceleration modules include motion compensation, inverse transform and loop filtering. By comparing the optimized decoder with the committee reference decoder of Joint Video Team (JVT), the experimental results show improvement on the decoding throughput by 7 to 8 times. On an ARM966 board, the optimized software without hardware acceleration can achieve a decoding rate up to 5.9 frames per second (fps) for QCIF video source. The overall throughput is improved by another 27% to 7.4 fps on the average and up to 11.5 fps for slow motion video sequences. Finally, we provide a theoretical analysis of the ideal performance of the proposed decoder.