Communicating sequential processes
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Statecharts: A visual formalism for complex systems
Science of Computer Programming
Communication and concurrency
Proceedings of the international workshop on Automatic verification methods for finite state systems
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Software timing analysis using HW/SW cosimulation and instruction set simulator
Proceedings of the 6th international workshop on Hardware/software codesign
Multilanguage design of heterogeneous systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
VHDL design representation and synthesis (2nd ed.)
VHDL design representation and synthesis (2nd ed.)
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Proceedings of the 37th Annual Design Automation Conference
embedded system design with multiple languages: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Methodology for hardware/software co-verification in C/C++ (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
The Complete VERILOG Book
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
Art of Software Testing
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices
Computer
System-on-a-Chip Cosimulation and Compilation
IEEE Design & Test
Codesign of Embedded Systems: Status and Trends
IEEE Design & Test
Platform-Based Design and Software Design Methodology for Embedded Systems
IEEE Design & Test
Automatic Symbolic Verification of Embedded Systems
IEEE Transactions on Software Engineering
A Synchronous Calculus of Relative Frequency
CONCUR '90 Proceedings of the Theories of Concurrency: Unification and Extension
The STATEMATE Verification Environment - Making It Real
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
IF-2.0: A Validation Environment for Component-Based Real-Time Systems
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Verification of the Futurebus+ Cache Coherence Protocol
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Hierarchical Modeling and Verification of Embedded Systems
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Automated Validation of Distributed Software Using the IF Environment
NCA '01 Proceedings of the IEEE International Symposium on Network Computing and Applications (NCA'01)
OOPSLA '03 Companion of the 18th annual ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Ambient intelligence: a computational platform perspective
Ambient intelligence
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exploring SW Performance Using SoC Transaction-Level Modeling
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
A Timing-Accurate HW/SW Co-Simulation of an ISS with SystemC
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Timed HW-SW cosimulation using native execution of OS and application SW
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Managing embedded systems complexity with aspect-oriented model-driven engineering
ACM Transactions on Embedded Computing Systems (TECS)
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Embedded Systems, by their nature, constitute a meeting point for communities with extremely different background. In particular, the high demands for quality and reliability for embedded systems have led to complementary quality assurance efforts: hardware engineers have developed techniques for dynamic verification in terms of co-simulation, which, in particular, addresses the different nature of hardware and software components. Thus these techniques are tailored for the transactional level, which comprises dedicated models for the hardware and the software parts. On the other hand, there is a bulk of work on formal verification techniques, which typically address higher levels of abstraction. These techniques are exhaustive in the sense that they cover all the infinite possible paths of their models, however at the price of neglecting many of the low-level aspects treated by co-simulation. It is the goal of this paper to increase the mutual understanding between these communities and to animate research at this exciting borderline.