Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Verification of the Futurebus+ cache coherence protocol
Formal Methods in System Design - Special issue on symbolic model checking
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification in a commercial setting
DAC '97 Proceedings of the 34th annual Design Automation Conference
Expressing interesting properties of programs in propositional temporal logic
POPL '86 Proceedings of the 13th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
A New Approach for the Verification of Cache Coherence Protocols
IEEE Transactions on Parallel and Distributed Systems
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Applying Formal Verification with Protocol Compiler
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Abstraction Refinement for Large Scale Model Checking (Series on Integrated Circuits and Systems)
Abstraction Refinement for Large Scale Model Checking (Series on Integrated Circuits and Systems)
Formal Verification of a Public-Domain DDR2 Controller Design
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Formal verification of an ASIC ethernet switch block
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Using coverage to deploy formal verification in a simulation world
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
| Hi-index | 0.00 |
Model checking tools are gaining traction as a practical formal verification solution for industrial designs. However, the use of absraction models is key to overcoming complexity barriers in applying these tools. Coverage has been a useful metric to determine when simulation-based verification is complete. In this paper, we show how similar coverage metrics can be used to determine the completeness of a formal verification setup. We also show how coverage can be used to determine effectivness of different abstraction models are. This methodology can be used to set formal verification goals, and to measure the progress of the work, thereby placing formal verification in a chip design schedule. We use a real-world design with a large state space, and present quantitative coverage metrics to illustrate the methodology, and its benefits for faster run-time, faster discovery of bugs, and higher coverage.