Facilitating unreachable code diagnosis and debugging
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Using coverage to deploy formal verification in a simulation world
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Planning for end-to-end formal using simulation-based coverage: invited tutorial
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
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This paper demonstrates a formal verification- planning process and presents associated verification strategy that we believe is an essential (yet often neglected) step in an ASIC or SoC functional formal verification flow. Our contribution is to present a way to apply the verification planning process and a set of abstraction techniques on a non-trivial open-source example (the Sun OpenSPARCTM DDR2 controller). The process and verification strategy can be applied to DDR2 controllers in particular and generalized for other designs.