VLSI implementation of rake receiver for IS-95 CDMA Testbed using FPGA
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Multiuser Detection
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers
Journal of VLSI Signal Processing Systems
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
A rapid prototyping environment for wireless communication embedded systems
EURASIP Journal on Applied Signal Processing
IEEE Transactions on Wireless Communications
Multi-user detection for DS-CDMA communications
IEEE Communications Magazine
The 3GPP proposal for IMT-2000
IEEE Communications Magazine
Journal of VLSI Signal Processing Systems
VLSI Implementation of an Adaptive Multiuser Detector for Multirate WCDMA Systems
Journal of Signal Processing Systems
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The VLSI architecture targeted on FPGAs of a multiuser detector based on a cascade of adaptive filters for asynchronous WCDMA systems is presented. The algorithm is briefly described. This paper focuses mainly on real-time implementation. Also, it focuses on a design methodology exploiting the modern technology of programmable logic and overcoming the limitations of commercial tools. The dedicated architecture based on a regular structure of processors and a special structure of memory exploiting FPGA architecture maximizes the processing rate. The proposed architecture was validated using synthesized data in UMTS communication scenarios. The performance goal is to maximize the number of users of different WCDMA data traffics. This dedicated architecture can be used as an intellectual property (IP) core processing an MUD function in the system-on-programmable-chip (SOPC) of UMTS systems. The targeted FPGA components are Virtex-II and Virtex-II Pro families of Xilinx.