VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers

  • Authors:

  • Gang Xu;Sridhar Rajagopal;Joseph R. Cavallaro;Behnaam Aazhang

  • Affiliations:

  • Department of Electrical and Computer Engineering, Rice University, 6100 Main St., Houston TX 77005, USA;Department of Electrical and Computer Engineering, Rice University, 6100 Main St., Houston TX 77005, USA;Department of Electrical and Computer Engineering, Rice University, 6100 Main St., Houston TX 77005, USA;Department of Electrical and Computer Engineering, Rice University, 6100 Main St., Houston TX 77005, USA

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2002

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Abstract

The multistage detection algorithm has been proposed as an effective interference cancellation scheme for next generation Wideband Code Division Multiple Access (W-CDMA) base stations. In this paper, we propose a real-time VLSI implementation of this detection algorithm in the uplink system, where we have achieved both high performance in interference cancellation and computational efficiency. When interference cancellation converges, the difference of the detection vectors between two consecutive stages is mostly zero. Under the assumption of BPSK modulation, the differences between the bit estimates from consecutive stages are 0 and ±2. Bypassing the zero terms saves computations. Multiplication by ±2 can be easily implemented in hardware as arithmetic shifts. However, the convergence of the algorithm is dependent on the number of users, the interference and the signal to noise ratio and hence, the detection has a variable execution time. By using just two stages of the differencing detector, we achieve predictable execution time with performance equivalent to at least eight stages of the regular multistage detector. A VLSI implementation of the differencing multistage detector is built to demonstrate the computational savings and the real-time performance potential. The detector, handling up to eight users with 12-bit fixed point precision, was fabricated using a 1.2 μm CMOS technology and can process 190 Kbps/user for 8 users.