A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival

Authors:
Naofumi Takagi;Takashi Horiyama
Affiliations:
Nagoya Univ., Nagoya, Japan;Kyoto Univ., Kyoto, Japan
Venue:
IEEE Transactions on Computers
Year:
1999

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Abstract

An efficient parallel adder under left-to-right input arrival is proposed. Making full use of the delay of the input arrival, it produces the sum within a small constant delay after the arrival of the final bits. Its amount of hardware is proportional to the operand length. It can be applied to the quotient conversion in an array divider